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| 5X7 mm SMD, 3.3V, CMOS Frequency Range: Frequency Stability: Temperature Range: Operating: (Option M) (Option X) Storage: Input Voltage: Input Current: Output: Symmetry: Rise/Fall Time: Logic: Load: Jitter: Aging: CPLL-018 Model ree dF ea oHS nt L R plia m Co 1.544MHz to 200MHz 25ppm, 50ppm, 100ppm Programmable Clock Oscillator PLL Based Design 0C to 70C -20C to 70C -40C to 85C Designed to meet today's -55C to 120C requirements for economical 3.3V 0.3V 3.3V applications. Available 45mA Max on 16mm tape and reel in CMOS quantities of 1K. 40/60% Max @ 50% Vdd 10ns Max @ 20/% to 80% Vdd "0" = 80% Vdd Max "1" = 90% Vdd Min 15pF 150pS pk-pk Max <3ppm 1st/yr, <1ppm every year hereafter SUGGESTED PAD LAYOUT 0.055 Typ (1.40 Typ) #1 #2 #3 0.045 0.008 (1.14 0.20) 0.165 (4.19) 0.071 SQ (1.80) Dimensions inches (mm) All dimensions are Max unless otherwise specified. 0.295 Max (7.50) P/N Freq DC Denotes pad 1 0.204 Max (5.02) 0.075 Max (1.80) #4 0.200 0.005 (5.08 0.13) 0.200 (5.08) 0.01uF Bypass Capacitor Recommended RECOMMENDED REFLOW SOLDERING PROFILE TEMPERATURE 260C 217C 200C 150C Ramp-Up 3C/Sec Max. Critical Temperature Zone Ramp-Down 6C/Sec. Crystek Part Number Guide CPLL-018 X- 25 - 200.000 #1 #2 #3 #4 #5 #1 Crystek Clock PLL Osc. #2 Model #3 Temp. Range: Blank= 0/70C, M= -20/70C, X= -40/85C #4 Stability: (see Table 1) #5 Frequency in MHz: 3 or 6 decimal places Stability Indicator Blank (std) 25 50 100ppm 25ppm 50ppm Preheat 180 Secs. Max. 8 Minutes Max. 90 Secs. Max. Example: CPLL-018X-25-200.000 = 3.3V Tristate, -40/85C, 25ppm, 200.000 MHz CPLL-018-50-19.660800 = 3.3V Tristate, 0/70, 50ppm, 19.660800 MHz Table 1 260C for 10 Secs. Max. NOTE: Reflow Profile with 240C peak also acceptable. mA M OUT pin 4 Vdd OUT Tri-State Function Function pin 1 Open "1" level 2.4V Min "0" level 0.4V Max Output pin Active Active High Z pin 3 OSC. GND PWR Supply O/P Load incl Probe Cl VM Bypass Cap. pin 1 pin 2 High Impedance GND or "LOW" Oscillation OPEN or "HIGH" Specifications subject to change without notice. TD-040405 Rev.C |
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